Integrated circuit (IC) design in the deep-submicron process nodes (e.g., 32 nm and beyond) involves a number of non-trivial challenges, and IC packaging has faced particular complications, such as those with respect to flip-chip packages. Continued package scaling will tend to exacerbate such problems.
These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the claimed invention to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques/structure may have less than perfect straight lines, right angles, etc., and some features may have surface topology or otherwise be non-smooth, given real world limitations of IC fabrication/processing. In short, the figures are provided merely to show example structures.